Printed circuit board and method of manufacturing the same

ABSTRACT

A method of manufacturing a printed circuit board is provided. The method includes preliminarily forming a plurality of test pattern layers for detecting the depth of an inner layer in a multilayer printed circuit board such that at least a part of a lower test pattern layer is not overlaid with any upper test pattern layer when viewed from a drill entrance side, and preliminarily forming a surface conductor layer; applying a voltage between the surface conductor layer and the test pattern layers; performing drilling toward one test pattern layer, and detecting a current produced when the drill comes into contact with the test pattern to measure the depth of the layer (D 1 ); performing drilling toward the other test pattern layer, and measuring the depth of the layer (D 2 ); and performing drilling up to just before the conductor-wiring layer based on a depth calculated from D 1  and D 2.

BACKGROUND OF THE INVENTION

The present invention relates to a method of manufacturing a printedcircuit board for improving signal delay and impedance mismatching, anda printed circuit board suitable for the method of manufacturing thesame. More particularly, the present invention relates to a method ofshortening a stub of the printed circuit board.

In order to mount an electronic component, such as a LSI (large-scaleintegrated circuit), to a multilayer printed circuit board, athrough-hole is formed and conductive plating is applied to thethrough-hole, to provide a terminal for connecting with a predeterminedinner conductor-wiring layer. However, since a plated portion of thethrough-hole is longer than the distance to the target conductor-wiringlayer, there arise problems in impedance mismatching, signal delay, andwaveform distortion unless the overlong portion (hereinafter referred toas stub) is shortened.

Therefore, it is necessary to perform drilling (hereinafter referred toas back-drilling) from the back side up to just before theconductor-wiring layer to remove the stub of plating by use of a drillhaving a diameter slightly larger than that of the through-hole. Thereis an increasing need for this process with an increase ofhigh-frequency printed circuit boards in recent years.

In the processing, controlling the depth of back-drilling has a problem.A printed circuit board is generally formed by compressing with heatresin layers and conductive wiring layers stacked alternately, which maycause a variation in the thickness of each layer and board, whichresults in a depth variation ranging from 60 to 100 μm of the positionof the conductive wiring layer.

To cope with the above problem, the following method is devised. Adetecting portion of a detection pattern is formed just before thetarget conductor-wiring layer and a voltage is applied between thedetection pattern and a drill for back-drilling. Thereby a current flowswhen the drill comes in contact with the detecting portion, then theback-drilling is terminated. (for example, refer to JP-A-2006-173146(FIG. 1, Detecting portion 35) or JP-A-2005-116945 (FIG. 7, Currentdetection layer 16-1))

However, with the above-mentioned conventional method of using detectingportions, a detection pattern becomes complicated and, accordingly, thenumber of layers increases, which may result in an increase in thematerial cost in some cases. Further, there may be a hole around which adetecting portion cannot be formed at all.

SUMMARY OF THE INVENTION

In order to solve the above-mentioned problem, the present inventionprovides a method of manufacturing a printed circuit board, for forminga through-hole for connecting a predetermined conductor-wiring layer ofa multilayer printed circuit board having a plurality of conductorlayers and insulating layers, applying conductive plating to thethrough-hole, and removing an overlong plated portion by drilling up tothe vicinity of the conductor-wiring layer. The method comprising thesteps of: preliminarily forming a plurality of test pattern layers fordetecting the depth of an inner layer in the multilayer printed circuitboard such that at least a part of a lower test pattern layer is notoverlaid with any upper test pattern layer when viewed from a drillentrance side, and a surface conductor layer such that all the testpattern layers are overlaid with it; applying a voltage to two selectedtest pattern layers in the vicinity of a region subjected to thedrilling, such that the depths of the two selected test pattern layersare near the depth of the conductor-wiring layer; performing drillingtoward one of the selected test pattern layers by use of a drill for thedrilling, and detecting a current produced when the drill comes intocontact with the relevant test pattern to measure the depth of the layer(D1); performing drilling toward the other test pattern layer by use ofthe drill, and detecting a current produced when the drill comes intocontact with the relevant test pattern to measure the depth of the layer(D2); and performing the drilling by use of the drill up to just beforethe conductor-wiring layer with reference to a depth calculated from theD1 and D2.

Further, the present invention provides a multilayer printed circuitboard having a plurality of conductor layers and insulating layers,wherein a plurality of test pattern layers for detecting the depth of aninner layer in the multilayer printed circuit board are preliminarilyformed such that at least a part of a lower test pattern layer is notoverlaid with any upper test pattern layer when viewed from a drillentrance side, and a surface conductor layer is preliminarily formedsuch that all the test pattern layers are overlaid with it.

As explained above, in accordance with the present invention, it ispossible to perform high-precision back-drilling by use of a simple testpattern.

BRIEF DESCRIPTION OF THE INVENTION

FIG. 1 is a plan view showing an example of a printed circuit boardsuitable for a method of manufacturing the same according to the presentinvention.

FIG. 2 is a cross-sectional view taken along the A-A line of FIG. 1.

FIG. 3 is a cross-sectional view taken along the B-B line of FIG. 1.

FIG. 4 is an enlarged fragmentary sectional view showing a first processof the method of manufacturing a printed circuit board according to thepresent invention.

FIG. 5 is an enlarged fragmentary sectional view showing a secondprocess of the method of manufacturing a printed circuit board accordingto the present invention.

FIG. 6 is an enlarged fragmentary sectional view showing a third processof the method of manufacturing a printed circuit board according to thepresent invention.

FIG. 7 is an enlarged fragmentary sectional view showing a fourthprocess of the method of manufacturing a printed circuit board accordingto the present invention.

FIG. 8 is an enlarged fragmentary sectional view showing a status wherethe method of manufacturing a printed circuit board according to thepresent invention is completed.

FIG. 9 is a plan view showing a second embodiment of a printed circuitboard suitable for the method of manufacturing the same according to thepresent invention.

FIG. 10 is a sectional view taken along the C-C line of FIG. 9.

FIG. 11 is a sectional view taken along the D-D line of FIG. 9.

FIG. 12 is a plan view showing a third embodiment of a printed circuitboard suitable for the method of manufacturing the same according to thepresent invention.

FIG. 13 is a plan view showing a fourth embodiment of a printed circuitboard suitable for the method of manufacturing the same according to thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

A method of manufacturing a printed circuit board according to thepresent invention and an embodiment of the printed circuit board will beexplained below with reference to the accompanying drawings.

FIG. 1 is a plan view showing an example of a printed circuit boardsuitable for a method of manufacturing the same according to the presentinvention, FIG. 2 is a cross-sectional view taken along the A-A line ofFIG. 1, and FIG. 3 is a cross-sectional view taken along the B-B line ofFIG. 1. A printed circuit board 1 has conductor-wiring layers 10 whichare separated by insulating layers 11 and connected by a plated innerlayer via-hole 12 or the like. Terminals 6 a, 6 b, etc. for connectingelectronic components, etc. are concentrated in one part on the printedcircuit board 1 to form back-drilling portions 5 a and 5 b. In theprinted circuit board according to the present invention, two testpattern layers 3 and 4 are formed such that at least a part of the testpattern layer 4 is not overlaid with the test pattern layer 3, anddisposed in the vicinity of the back-drilling portions 5 a and 5 b, nearthe depth of a target inner conductor-wiring layer. A surface conductorlayer 2 is formed such that both test pattern layers 3 and 4 areoverlaid with it. In this example, a part of the surface conductor layer2 is pulled out as a surface conductor layer electrode 21, and a part ofeach of the test pattern layers 3 and 4 is pulled out below the testpattern layer electrode 22 and then connected with a platedthrough-hole. A power source (not shown) is connected between thesurface conductor layer electrode 21 and the test pattern layerelectrode 22, and a voltage (about 5V) is applied therebetween. Whenconduction occurs between the surface conductor layer 2 and one of thetest pattern layers 3 and 4 by a drill, a current flows therebetween andis detected by a detector (not shown), thus recognizing that the drillhas reached the relevant test pattern layer. Points 3 a to 3 f and 4 ato 4 f are used to measure the depths of respective test pattern layers(hereinafter referred to as depth measuring points).

Back-drilling related to the method of manufacturing the printed circuitboard according to the present invention will be explained below withreference to the terminals 6 a and 6 b of the back-drilling portion 5 a.FIGS. 4 to 8 are enlarged fragmentary sectional views of the relevantportions, each sequentially showing the progress of back-drillingprocess in this order.

First, drilling is performed to the depth measuring point 3 a by use ofa drill 7 for back-drilling, and then the depth of the test patternlayer 3 (D1) is measured (refer to FIG. 4).

Then, drilling is performed to the depth measuring point 4 a by use ofthe drill 7, and then the depth of the test pattern layer 4 (D2) ismeasured (refer to FIG. 5).

Subsequently, the same measurements are performed also for othermeasuring points 3 b and 4 b shown in FIG. 1, and the obtained depths ofthe test pattern layers are averaged to calculate an intermediate depthof the test pattern layers 3 and 4. Here, a weighted average may be usedfor the calculation.

Then, using the calculated intermediate depth of the test pattern layers3 and 4 as a standard, the depth of a target conductor-wiring layer 10 afor the terminal 6 a is calculated (estimated), and the drilling depthof the drill 7 is determined to perform drilling, thus removing a platedlayer (refer to FIG. 6).

Similarly, the depth of a target conductor-wiring layer 10 b for theterminal 6 b is calculated (estimated) by adding a likely thickness of alayer, the drilling depth of the drill 7 is determined to performdrilling, thus removing a plated layer (refer to FIG. 7).

FIG. 8 shows a state where back-drilling for the terminals 6 a and 6 bis completed. In this example, the measuring points 3 a and 4 a arearranged in line with the terminals 6 a and 6 b for the convenience ofexplanation; however, they are not necessarily be in line as long as themeasuring points 3 a and 4 a are formed above the test pattern layers 3and 4, respectively.

Further, if the drilling portion is large like a back-drilling portion 5b, it is possible to prevent degradation of the depth measurementaccuracy by providing four measuring points for each test pattern, forexample, measuring points 3 c to 3 f and 4 c to 4 f.

First Embodiment

FIG. 1 is a plan view showing an example of a printed circuit boardsuitable for a method of manufacturing the same according to the presentinvention, FIG. 2 is a cross-sectional view taken along the A-A line ofFIG. 1, and FIG. 3 is a cross-sectional view taken along the B-B line ofFIG. 1. Explanations of FIGS. 1 to 3 will be omitted because they havealready been explained earlier. With the printed circuit board 1according to the present embodiment, the test pattern layer 4 having alarge width is formed immediately below the test pattern layer 3, andboth pattern layers are formed in the vicinity of the back-drillingportions 5 a and 5 b, and disposed near the depth of a target innerconductor-wiring layer. A surface conductor layer 2 is formed such thatboth test pattern layers 3 and 4 are overlaid with it.

Since the test pattern layers 3 and 4 can be formed simultaneously withcorresponding conductor-wiring layers 10 in a manufacturing process ofan ordinary printed circuit board, there is no difficulty in themanufacturing method. Further, the test pattern layers 3 and 4 can beused also as a common electrode or a ground after completion of theprinted circuit board because it is only necessary that the test patternlayers 3 and 4 are electrically insulated from the surface conductorlayer 2.

Second Embodiment

FIG. 9 is a plan view showing a second embodiment of a printed circuitboard suitable for the method of manufacturing the same according to thepresent invention, FIG. 10 is a sectional view taken along the C-C lineof FIG. 9, and FIG. 11 is a sectional view taken along the D-D line ofFIG. 9. In the present embodiment, four test pattern layers 30, 40, 41,and 42 are formed such that at least a part of a lower test patternlayer is not overlaid with any upper test pattern layer, in the vicinityof the back-drilling portions 5 a and 5 b, where the test pattern layersdo not overlay one another at all in this embodiment, and disposed nearthe depth of a target inner conductor-wiring layer. A surface conductorlayer 20 is formed such that all the test pattern layers 30, 40, 41, and42 are overlaid with it. In the present embodiment, a part of surfaceconductor layer 20 is pulled out as a surface conductor layer electrode201, and a part of each of the test pattern layers 30, 40, 41, and 42 ispulled out below the test pattern layer electrode 202 and then connectedwith a plated through-hole. A power source (not shown) is connectedbetween the surface conductor layer electrode 201 and the test patternlayer electrode 202, and a voltage (about 5V) is applied therebetween.When conduction occurs between the surface conductor layer 20 and one ofthe test pattern layers 30, 40, 41, and 42 by drilling, a current flowstherebetween and is detected by a detector (not shown), thus recognizingthat the drill has reached the relevant test pattern layer. Here, points30 a to 30 f, 40 a to 40 f, 41 a to 41 f, and 42 a to 42 f are used tomeasure the depths of respective test pattern layers.

The present embodiment is effective when target conductor-wiring layers10 c and 10 d for terminals 6 c and 6 d, respectively, of aback-drilling portion 50 a are separated from each other by twoinsulating layers. That is, it is preferable to perform back-drilling ofthe terminal 6 c regarding the conductor-wiring layer 10 c as a targetbased on a depth standard measured using the test pattern layers 30 and40, and back-drilling of the terminal 6 d regarding the conductor-wiringlayer 10 d as a target based on a depth standard measured using the testpattern layers 41 and 42. This makes it possible to prevent degradationof the depth accuracy in a case where a target conductor layer is farfrom a depth standard.

Although four test pattern layers are used in the present embodiment,only three test pattern layers 30, 40, and 41 may be used if there isnot a large difference in depth of the target conductor-wiring layers.In this case, it is possible to obtain a depth standard by use of thetest pattern layers 30 and 40, and another depth standard by use of thetest pattern layers 40 and 41.

Further, unlike the first embodiment, the present embodiment uses thetest pattern layers 30, 40, 41, and 42 that do not overlay one anotherwhen viewed from the top (the back) and the bottom (the front). In thiscase, however, if a surface conductor layer, a surface conductor layerelectrode, and a test pattern electrode are formed also on the frontside, it is possible to perform back-drilling of the same board not onlyfrom the back side but also from the front side.

Further, when back-drillings of test pattern layers 30 and 40 areperformed from the back side and the test pattern layer 41 and 42 fromthe front side, it is not necessary to make arrangements such that thetest pattern layers 30, 40, 41, and 42 do not overlay one another. It isonly necessary to make arrangements such that a part of the test patternlayer 40 is not overlaid with the test pattern layer 30 when viewed fromthe back side and a part of the test pattern layer 41 is not overlaidwith the test pattern layer 42 when viewed from the front side.

Third Embodiment

FIG. 12 is a plan view showing a third embodiment of a printed circuitboard suitable for the method of manufacturing the same according to thepresent invention. Portions of FIG. 12 assigned the same referencenumeral as FIG. 1 are the same as those of FIG. 1 and thereforeexplanations thereof will be omitted. In the present embodiment, asurface conductor layer 2 and test pattern layers 3 and 4 are arrangedso as to surround a large back-drilling portion 5 b. As seen from FIG.12, this configuration makes it easy to arrange measuring points 3 c to3 f and 4 c to 4 f nearer to the back-drilling portion 5 b.

Fourth Embodiment

FIG. 13 is a plan view showing a fourth embodiment of a printed circuitboard suitable for the method of manufacturing the same according to thepresent invention. Portions of FIG. 13 assigned the same referencenumeral as FIG. 1 are the same as those of FIG. 1 and thereforeexplanations thereof will be omitted. In the present embodiment, asurface conductor layer 2 and test pattern layers 3 and 4 are arrangedso as to surround a large back-drilling portion 5 b and in a latticepattern. As seen from FIG. 13, this configuration makes it easy toarrange measuring points 3 c to 3 f and 4 c to 4 f nearer to theback-drilling portion 5 b.

The invention claimed is:
 1. A method of manufacturing a printed circuitboard for forming a through-hole for connecting a predeterminedconductor-wiring layer of a multilayer printed circuit board having aplurality of conductor layers and insulating layers, applying conductiveplating to the through-hole, and removing an overlong plated portion bydrilling up to the vicinity of the conductor-wiring layer, the methodcomprising the steps of: preliminarily forming a plurality of testpattern layers for detecting the depth of an inner layer in themultilayer printed circuit board such that at least a part of a lowertest pattern layer is not overlaid with any upper test pattern layerwhen viewed from a drill entrance side, and a surface conductor layersuch that all the test pattern layers are overlaid with it; applying avoltage to two selected test pattern layers in the vicinity of a regionsubjected to the drilling, the depths of the two test pattern layersbeing near the depth of the conductor-wiring layer; performing a firstdrilling toward one of the selected test pattern layers by use of adrill for the drilling, and detecting a current produced when the drillcomes into contact with the relevant test pattern to measure the depthof the layer (D1); performing a second drilling toward the other testpattern layer by use of the drill, and detecting a current produced whenthe drill comes into contact with the relevant test pattern to measurethe depth of the layer (D2); and performing a third drilling by use ofthe drill up to just before the conductor-wiring layer based on a depthcalculated from the D1 and D2.
 2. The method of manufacturing a printedcircuit board according to claim 1, wherein the depth calculated fromthe D1 and D2 is an average of the D1 and D2.
 3. The method ofmanufacturing a printed circuit board according to claim 1, wherein theplurality of test pattern layers are all of the plurality of testpattern layers.
 4. The method of manufacturing a printed circuit boardaccording to claim 1, wherein the first drilling is performed at adifferent lateral position than the third drilling.
 5. The method ofmanufacturing a printed circuit board according to claim 1, wherein thesecond drilling is performed at a different lateral position than thethird drilling.
 6. The method of manufacturing a printed circuit boardaccording to claim 1, wherein the first drilling is performed at adifferent lateral position than the second drilling.
 7. The method ofmanufacturing a printed circuit board according to claim 1, wherein thefirst, second, and third drillings are performed at different lateralpositions.